1. Field of the Invention
The invention relates to a solid-state image pickup device having photoreceiving elements and, more particularly, to a solid-state image pickup device which can add signals from photoreceiving elements.
2. Related Background Art
A number of solid-state image pickup devices in each of which pixels including photoelectric conversion units are one-dimensionally or two-dimensionally arranged are used in digital cameras, video cameras, copying apparatuses, facsimile apparatuses, and the like. As solid-state image pickup devices, there are an amplifying type solid-state image pickup device such as CCD image pickup device, CMOS image pickup device, and the like.
In association with an increase in the number of pixels of an image sensor such as a solid-state image pickup device, in recent years, not only the conventional usage where signals of all pixels of the image sensor are always simply sequentially outputted but also usage where the signals of only a part of the pixels are outputted from the image sensor as necessary or a using method whereby usage where after the signals of the pixels are processed to a certain extent, they are outputted from the image sensor have been in high demand. For example, addition of the signals of the adjacent pixels and outputting of an addition signal from the image sensor if often executed for a better color process, resolution conversion, and the like. A method of reducing random noises by adding and averaging the signals of a larger number of pixels in the image sensor is also used.
An adding method disclosed in JP-A-2000-106653 as a Japanese Patent is shown in FIG. 12. FIG. 12 is a diagram showing a schematic construction of a 2H-line memory+2H-line adder circuit. Second vertical signal lines 17 (17-1, 17-2, . . . ) are connected to first vertical signal lines 8 (8-1, 8-2, . . . ) through sampling and holding transistors (S/H transistors) 29 (29-1, 29-2, . . . ) and capacitors C1 (C1-1, C1-2, . . . ), respectively. Although only two first vertical signal lines 8 are shown for simplicity of the drawing, a plurality of first vertical signal lines 8 are actually arranged in the lateral direction. Two sets of serial connection are connected to the second vertical signal lines 17 (17-1, 17-2, . . . ): that is, the serial connection of transistors 23 (23-1, 23-2, . . . ) and capacitors C2 (C2-1, C2-2, . . . ); and the serial connection of transistors 26 (26-1, 26-2, . . . ) and capacitors C3 (C3-1, C3-2, . . . ). A signal voltage of the 2Nth row is accumulated into the capacitor C2 through the transistor 23. A signal voltage of the (2N+1)th row is accumulated into the capacitor C3 through the transistor 26. The signal voltage of the 2Nth row and that of the (2N+1)th row are added by the second vertical signal line 17.
An adder circuit disclosed in JP-A-2000-261728 as a Japanese Patent is shown in FIG. 13. Signal components are accumulated into storage capacitors 43 and 49 from vertical output lines connected to the pixels through transfer switches 41 and 48, respectively. At the next timing, signal components of the pixels of another row are accumulated into a storage capacitor 45 through a transfer switch 42. After that, by turning on transfer switches 46, 47, and 50 by a control signal from a shift register 61, an addition component of the pixel signals of the two vertical output lines can be obtained in a horizontal output line 62. At this time, in FIG. 13, with respect to the signal components of the pixels of other rows, since the signal in the storage capacitor 45 is added together with the signal component in the storage capacitor 43, the added signal component of at least three pixels can be obtained.
In the conventional addition averaging means, however, the signals in the horizontal direction are added after the signals in the vertical direction are added. Therefore, in the case of adding the signal components of (m pixels in the horizontal direction)×(n pixels in the vertical direction) in a pixel array of (H columns×V rows), (n×H) sampling and holding (S/H) capacitors [in the case of the 2×2 addition, 2H S/H capacitors; in the case of the 3×3 addition, 3H S/H capacitors; . . . ] are necessary. There is, consequently, such a problem that the more a number of addition pixels exist in the vertical direction, the more a number of S/H capacitors increases are necessary, so that a size of the adder circuit increases.